Low Voltage Differential Signaling (LVDS) is a low swing, differential signaling technology that facilitates high speed data transmission. Its low swing and current mode driver outputs create low noise and consume relatively little power.
FIG. 1 illustrates a prior art LVDS driver 22 and receiver 24 connected via differential lines 25. A 100 Ohm differential impedance 26 is placed between the lines 25. The driver 22 includes a current source 27 that drives one of the differential lines 25. The receiver 24 has a high DC impedance (it does not source or sink DC current), so the majority of driver current flows across the 100 Ohm termination resistor 26 generating, in this embodiment, approximately 350 mV across the inputs of the receiver 24. When the opposite transistors of the driver 22 (the “−” transistors instead of the “+” transistors) are activated, current flows in the opposite direction. In this way, valid digital high and low states are transported.
The differential data transmission method used in LVDS is less susceptible to common-mode noise than single-ended schemes. Differential transmission conveys information using two wires with opposite current/voltage swings, instead of one wire used in single-ended methods. The advantage of the differential approach is that noise is coupled onto the two wires in a common mode (the noise appears on both lines equally) and is thus rejected by the receiver 24, which looks only at the difference between the two signals. The differential signals also tend to radiate less noise than single-ended signals, due to the canceling of magnetic fields. In addition, the current mode drive is not prone to ringing and switching spikes, thereby further reducing noise.
Since LVDS reduces concerns about noise, it can use lower signal voltage swings. This advantage is crucial, because it is impossible to raise data rates and lower power consumption without using low voltage swings. The low swing nature of the driver means data can be switched very quickly. Since the driver is also current mode, very low power consumption across frequency is achieved since the power consumed by the load is substantially constant.
FIG. 2 illustrates an LVDS communication system 30 including a transmitter 32 and a receiver 34 linked by a channel 35. The transmitter 32 multiplexes a large number of channels (e.g., 21 or 28) onto the smaller width channel 35 (e.g., having 4 or 5 channels). A serializer or multiplexer 36 is used to perform this function. The opposite function is performed at the receiver 34. That is, a de-serializer or de-multiplexer 38 takes the signals from the smaller width channel 35 and applies them across a large number of channels (e.g., 21 or 28). The relatively small channel 35 is used to reduce board, connector, and/or cable costs. This technique also lowers power, noise, and electro-magnetic interference.
FIG. 3 illustrates a prior art multiplexer 36 with four parallel-load shift registers (register banks) 40A–40D. Register banks 40A–40D respectively receive signals from buses 41A–41D. Register banks 40A–40D respectively drive differential output signals to differential output drivers 42A–42D.
A control logic circuit 43 and a clock/phase locked loop circuit 44 are connected to a control signal bus 45. The clock/phase locked loop circuit 44 receives a standard rate clock signal and produces a clock signal at seven times the standard rate. This faster clock signal is applied to the control signal bus 45 to drive each register bank 40. The standard clock signal is applied to the output clock differential driver 42E.
In the disclosed embodiment, each bus 41 carries seven signals which are transmitted at seven times the standard clock rate over each LVDS channel 42A–42D. Since the multiplexing and de-multiplexing operations are complementary, only multiplexing operations are discussed, however it should be understood that the invention covers both multiplexing and de-multiplexing operations.
There are a number of problems associated with the multiplexer 36 of FIG. 3. Since the multiplexer 36 operates at seven times the speed of the system clock, it consumes a relatively large amount of power. In addition, it is relatively difficult to generate and distribute the higher speed clock.
In view of the foregoing, it would be highly desirable to provide an improved signal control technique for use in LVDS systems. Ideally, such a system would have a relatively simple clock architecture and would operate in a lower power mode.